Magnetically controlled logic cell

ABSTRACT

A magnetically controlled logic cell comprising a semiconductor substrate (1) coated with a dielectric film and containing four field-effect transistors; four current supply buses in contact with the transistors and arranged on the surface of the dielectric film (17), two of the buses in question being power supply buses (34, 35), the other two being output buses (36, 37); and a region insulated from the substrate by a layer of concealed dielectric and by side insulation, the region in question containing four contacts configured symmetrically in pairs and connected to said transistors, power supply buses (34, 35) and output buses (36, 37).

BACKGROUND OF THE INVENTION

The present invention relates to the field of microelectronics and moreparticularly to magnetically controlled integrated circuits and could beused for building up memory cells and in sensor control devices.

There are known magnetically controlled logic cells with operatingprinciple based on changing of output signal in effect with externalmagnetic field. They constitute devices comprising a transformer ofmagnetic field into electric signal and an electronic circuit ofprocessing the signal placed in a single semiconductor crystal. The mostcommon transformer of magnetic field into electric signal is a Hallelement, operating principle of which is based on developing the EMFbetween two contacts located on the opposite sides of a rectangularsemiconductor sample placed in the magnetic field, with electric currentrunning between two contacts located on another sides of thesemiconductor.

The EMF forming by the Hall element in a magnetically controlled logiccell is passed to the input of an integrated circuit and results informing the signal on circuit output which is, depending on theintensity of the magnetic field, corresponding to a logical 0 orlogical 1. The magnetically controlled cell with Hall element is usuallyproduces of silicon using the conventional epitaxial-planar technology(U.S. Pat. No. 3,816,766, M.cl.GIIC 11/40, publ. in 1974).

The common drawbacks of the existing magnetically controlled logic cellsis their insufficient magnetic sensitivity and high level of powerconsumption. The first leads to impossibility of using this logic cellin low intensity magnet fields (on the order of one milli-Tesla) withoutcomplicating of the electronic circuit, mostly by adding amplifyingstages. The second drawback is associated with high value of electriccurrent running through the Hall element in a state of waiting formagnetic signal. This drawback also considerably restricts the practicalapplication of the magnetically controlled logic cells.

The mentioned drawbacks are directly associated with the value ofelectric resistance of the Hall element. In the present invention it isproposed a design of the magnetically controlled logic cell whichprovides the increasing of the electric resistance of the Hall elementresulting in increasing of magnetic sensitivity and decreasing of powerconsumption.

SUMMARY OF THE INVENTION

It is an object of the present invention to increase the magneticsensitivity and to decrease the power consumption of the magneticallycontrolled logic cells.

This object is achieved by that way that the magnetically controlledlogic cell comprises a semiconductor substrate of the first typeconductivity, eight alloyed regions of the second type conductivitycreating in pairs drain and source regions of four field-effecttransistors, a dielectric film arranged on the surface of the substratehaving openings over each of the drain and source regions, eightconducting contact regions located over the drain and source regions ontheir surface and on the surface of the dielectric film, four conductinggate regions each situated on the surface of the dielectric film betweenthe drain and source regions of each transistor, four current supplybuses arranged on the surface of the dielectric film, the first of whichis adjoining the source regions of the first and second transistors andbeing a power supply bus, the second one is adjoining the source andgate regions of the third and fourth transistors and being a powersupply bus, the third one is adjoining the gate region of the firsttransistor, source regions of the second and fourth transistors andbeing an output bus, the fourth one is adjoining the gate region of thesecond transistor, source regions of the first and third transistors andbeing an output bus, the substrate of the first type conductivitycomprises a concealed dielectric region, insulating region arranged onthe perimeter of the concealed dielectric region and adjoining it andthe dielectric film, four highly alloyed regions of the first typeconductivity adjoining the insulating region and the concealeddielectric region and arranged in pairs and symmetrically in respect toeach other near the opposite sides of the region of the first typeconductivity created by the concealed dielectric region and insulatingregion, four conducting contacts to the highly alloyed regions of thefirst type conductivity and current conducting buses, the first one isadjoining the power supply bus and the contact to one of the highlyalloyed regions of the first type conductivity, the second one isadjoining another power supply bus and the opposite contact to anotherhighly alloyed region of the first type conductivity, the third one isadjoining the output bus and the contact of the second pair of thehighly alloyed regions of the first type conductivity, the fourth one isadjoining the opposite contact of the second pair of the highly alloyedregions of the first type conductivity and another output bus.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a topological diagram of the mangnetically controlled cell.

FIG. 2 is a cross-section of the layers (taken along line A--A in FIG.1).

FIG. 3 is an electric diagram of the magnetically controlled cell.

PREFERRED EMBODIMENT

The magnetically controlled logic cell comprises a semiconductorsubstrate of the first type conductivity--1 (produced, f.e., ofmonocrystalline silicon), eight alloyed regions of the second typeconductivity--2-9, a concealed dielectric region --10 (f.e., of silicondioxide, nitride or oxynitride), insulating region--11 (f.e., of silicondioxide or formed by p--n junction), a region of the fist typeconductivity--12 arranged on the perimeter of the concealed dielectricregion--10 and adjoining the surface of the semiconductor substrate--1and separated from the semiconductor substrate 1 by the concealeddielectric region 10 and insulating region 11, four highly alloyedregions of the first type conductivity--13-16 arranged symmetrically inpairs inside the region the first type conductivity 12 in the middle ofits each side and adjoining the region of the concealed dielectric 10and the insulating region 11, the dielectric film 17 arranged on thesurface of the semiconductor substrate 1 (f.e., of silicon dioxide),conducting contact regions--18-25 leading up to the alloyed regions 2-9of the second type conductivity and contact regions--26-29 leading up tothe highly alloyed regions 13-16 of the first type conductivity arrangedon the surface of the semiconductor substrate 1 the dielectric film 17,four conducting regions 30-33 and the current supply buses--34-37 and38-41 arranged on the surface of the dielectric film 17 (the contactregions, conducting regions, current supply buses are produced, f.e., ofaluminum).

The alloyed regions of the second type conductivity 2, 5, 6, 9constitute the sources and the alloyed regions of the second typeconductivity 3, 4 7, 8 constitute the drains of the four field-effecttransistors respectively. The conducting regions 30-33 being the gatesof these transistors. The region 12 separated from the semiconductorsubstrate 1 by the concealed dielectric 10 and semiconductor 11 regionsconstitutes the Hall element, and the highly alloyed regions of the fisttype conductivity 13-16 and the contact regions 26-29 being the contactsystem of the Hall element. The power supply bus 34 is connected throughthe contact 18 with the source 2 of the first transistor, through thecontact 21 with the source 5 of the second transistor and with help ofthe bus 39 with the contact 28 is connected to the Hall element. Thepower supply us 35 is connected with the source 6 (through the contact22) and with the gate 32 of the third transistor, with the source 9(through the contact 25), the gate 33 of the fourth transistor and, withhelp of the bus 38 with contact 29, is connected to the Hall elementwhich is opposite to the contact 28. The output bus 36 connects the gate30 of the first transistor, the drain 4 of the second transistor and thedrain 8 of the fourth transistor (through the contact 24) with thecontact 26 leading up to the Hall element (through the bus 40). Theoutput bus 37 connects the gate 31 of the second transistor, the drain 3of the first transistor (through the contact 19) and (through thecontact 23) the drain 7 of the third transistor (through the bus 41)with the contact 27 to the Hall element which is opposite the contact26.

The magnetically controlled logic cell comprises the Hall element (HE)being a controlling element and a symmetrical trigger with directcoupling being a control circuit comprising four transistors. And withthe transistors T3 and T4 used as load resistors for the transistors T1and T2.

The magnetically controlled logic cell functions in following way. Inthe initial state the transistor T1 is open, and the transistor T2 isclosed. On the output 37 there is a potential (signal) of high level, onthe output 36 there is a potential of low level. Electric current isrunning through the contacts 28-29 of the HE (so called, current of thewaiting state). Potential on the contacts 26-27 of the HE (in absence ofmagnetic field) is absent. Under the action of magnetic field thereoccurring Hall EMF on the HE output (contacts 26-27) which changes thepotential of the gate of the transistor T1. If the external magneticfield density B is greater then a curtain threshold level B_(thres), thetransistor T1 closes and in result of this the transistor T2 opens andthe cell output signal changes. When the external magentic field densityis decreasing to the level lover then the threshold level B_(thres), thetransistor T1 opens and the transistor T2 closes and the cell outputsignal is shifting to the initial level.

INDUSTRIAL APPLICABILITY

The advantages of the proposed magnetically controlled cell are theincreased magnetic sensibility (approximately up to 10 times) anddecreased power consumption (no less then in 2 times).

The fields of applicability of the magnetically controlled logic cellsare memory systems, ignition systems in car engines, PC and telephonenoncontact keyboards, control circuits of collectorless electric drives,navigation systems. In robot technology it is possible to design on thebasis of this circuit control devices for shifting, rotating andapproaching of an object. These cells are also applied in automation andcontrol systems, f.e., in control systems of metal-cutting andmetal-working machine tools. In home electric appliance they could beused for electric drives control, f.e., in washing machines, vacuumcleaners under the condition of changing load.

We claim:
 1. A magnetically controlled logic cell comprising asemiconductor substrate (1) of the first type conductivity, eightalloyed regions of the second type conductivity (2-9) creating in pairsdrain and source regions of four field-effect transistors, a dielectricfilm (17) arranged on the surface of the substrate having openings overeach of the drain and source regions, eight conducting contact regions(18-25) located over the drain and source regions on their surface andon the surface of the dielectric film (17), four conducting gate regions(30-33) each situated on the surface of the dielectric film (17) betweenthe drain and source regions of each transistor, four current supplybuses (34-37) arranged on the surface of the dielectric film (17) thefirst (34) of which is adjoining the source regions of the first andsecond transistors and being a power supply bus, the second one (35) isadjoining the source and gate regions of the third and fourthtransistors and being a power supply bus, the third one (36) isadjoining the gate region of the first transistor, source regions of thesecond and fourth transistors and being an output bus, the fourth one(37) is adjoining the gate region of the second transistor, drainregions of the first and third transistors and being an output bus,characterized in, that the substrate of the first type conductivitycomprises a concealed dielectric region (10) an insulating region (11)arranged on the perimeter of the concealed dielectric and adjoining itand the dielectric film (17), four highly alloyed regions of the firsttype conductivity (13-16) adjoining the insulating region (11) and theconcealed dielectric region (10) and arranged symmetrically in pairs inrespect to each other near the opposite sides of the region of the firsttype conductivity created by the concealed dielectric region (10) andinsulating region (11), four conducting contacts (26-29) to the highlyalloyed regions of the first type conductivity and current supply buses(38-41), the first one (39) of which is adjoining the power supply bus(34-35) and the contact of one of the highly alloyed regions of thefirst type conductivity, the second one (38) is adjoining another powersupply bus and the opposite contact of another highly alloyed region ofthe first type conductivity, the third one (40) is adjoining the outputbus (36) and the contact of the second pair of the highly alloyedregions of the first type conductivity, the fourth on (41) is adjoiningthe opposite contact of the second pair of the highly alloyed regionsand another output bus (37).